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6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 1 rev 2 april 201 4 f1953 datasheet g eneral d escription this document describes the specification for the idtf1953 digital step attenuator. the f1953 is part of a family of glitch - free tm dsas optimized for the demanding requirements of communications infrastructure. these devices are offered in a compact 4x4 qfn package with 50 impedances for ease of integration. c ompetitive a dvantage digital step attenuators are used in receivers and transmitters to provide gain control. the idtf1953 is a 6 - bit step attenuator optimized for these demanding applications. the silicon design has very low insertion loss and low distortion ( > + 6 0 dbm ip3 i .) the device has pinpoint accuracy and settles to final attenuation value within 400 nsec. most importantly, the f1953 includes idts g g l l i i t t c c h h - - f f r r e e e e t t m m technology which results in less than 0.5 db of overshoot ringing during msb transitions. this is in sta rk contrast to competing dsas that glitch as much as 10 db (see p. 10 . ) ? ? l l o o w w e e s s t t i i n n s s e e r r t t i i o o n n l l o o s s s s f f o o r r b b e e s s t t s s n n r r ? ? g g l l i i t t c c h h - - f f r r e e e e t t m m w w h h e e n n t t r r a a n n s s i i t t i i o o n n i i n n g g C C w w o o n n t t d d a a m m a a g g e e p p a a o o r r a a d d c c ? ? e e x x t t r r e e m m e e l l y y a a c c c c u u r r a a t t e e w w i i t t h h l l o o w w d d i i s s t t o o r r t t i i o o n n a pplications ? base station 2g, 3g , 4g, tdd radiocards ? repeaters and e911 systems ? digital pre - distortion ? point to point i nfrastructure ? public safety i nfrastructure ? wimax receivers and transmitters ? military systems , jtrs radios ? rfid handheld and portable readers ? cable infrastructure p art # m atrix part# freq range resolution / range control il pinout f19 50 150 - 4000 0.25 / 31.75 parallel & serial - 1. 3 pe 43702 pe43701 f195 1 100 - 4000 0. 50 / 31. 5 serial only - 1.2 hmc305 f1952 100 C 4000 0.50 / 15.5 serial only - 0.9 h mc305 f f 1 1 9 9 5 5 3 3 4 4 0 0 0 0 - - 4 4 0 0 0 0 0 0 0 0 . . 5 5 0 0 / / 3 3 1 1 . . 5 5 p p a a r r a a l l l l e e l l & & s s e e r r i i a a l l - - 1 1 . . 3 3 p p e e 4 4 3 3 0 0 2 2 d d a a t t - - 3 3 1 1 r r 5 5 f eatures ? glitch - free tm , < 0.6 db transient overshoot ? spurious free design ? 2.7 to 3.3 v supply ? attenuation error < 0. 5 db @ 2 ghz ? low insertion loss < 1. 4 db @ 2 ghz ? excellent linearity > + 60 dbm ip3 i ? fast settling time, < 400 nsec ? serial or parallel interface 31.5 db range ? stable integral non - linearity over temperature ? low power consumption < 200 ua ? integrated dc blocking capacitors ? drop - in r eplacement ? 4x4 mm thin qfn 20 pin package d evice b lock d iagram o rdering i nformation idt f1953ncg i8 0.8 mm height package green industrial temp range tape & reel omit idt prefix rf product line rf 1 bias v dd v mode dec d [ 5 : 0 ] 6 clk spi le data rf 2 glitch - free tm glitch - free tm
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 2 rev 2 april 201 4 f1953 datasheet a bsolute m aximum r atings v dd to gnd - 0.3v to +3.3 v d[5:0], data , clk, le , v mode - 0.3v to 3.6v rf input power ( rf 1 , rf 2 ) calibration and testing + 29 dbm rf input power ( rf 1, rf2 ) continuous rf operation +23 dbm ja (junction C ambient) + 50 c/w jc (junction C case ) the case is defined as the exposed paddle + 3 c/w operating temperature range (case temperature) t c = - 40c to + 100 c maximum junction temperature 14 0c storage temperature range - 65c to +150c lead temperature (soldering, 10s) . + 260 c stresses above those listed above may cause permanent damage to the device. f unctional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution this product features proprietary protection circuitry. however, it may be damaged if subjected to high energy esd. please use proper esd precautions when handling to avoid damage or loss of performance.
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 3 rev 2 april 201 4 f1953 datasheet idt f1953 s pecification ( 31.5 db range ) specifications apply at v dd = +3.0 v , f rf = 20 0 0mhz , t c = +25c, v mode > v i h ( serial mode) evkit losses are de - embedded (see p. 17 ) parameter comment sym. min typ max units logic input high clk, csb , sdi, sdo , rstb v ih 0 .7 xv dd v dd v logic input low clk, csb, sdi, sdo, rstb v il 0 .3 xv dd v logic current v mode , d[5:0] i ih, i il - 5 +5 a logic current le i ih, i il - 35 + 35 a supply voltage(s) main supply v dd 2.7 to 3.3 v supply current total v dd = 3v i dd 0 .16 0. 2 5 1 ma temperature range operating range (case) t c - 40 to +100 degc frequency range operating range f rf 400 to 4000 mhz rf1 ,rf2 return loss 20*log( s 11 ) , 20*log( s 22 ) s 11 , s 22 - 23 db minimum attenuation d[ 5 : 0] = [ 000000 ] a m in 1. 35 1.9 0 db m aximum attenuation d[ 5 : 0 ] = [ 111111 ] a max 32 . 0 32. 4 db minimum gain step least significant bit lsb 0. 50 db phase delta p hase change a min vs. a max 39 deg differential attn error between adjacent steps dnl 0.09 db integral attn error error vs. line (a min ref) to 13.5 db attn inl 1 0.2 0 0.60 db integral attn error error vs. line (a min ref) to 31.5 db attn inl 2 0. 47 0.75 db input ip3 d[5:0] = [000000 ] = a min d[5:0] = [011111 ] = a 15. 5 d[5:0] = [111111 ] = a max ? p in = +10 dbm per tone ? 50 mhz tone separation ip3i 1 ip3i 2 ip3i 3 +57 2 + 5 3 +53 + 66 +60 +60 dbm 0.1 db compression please note abs max p in on page 2 ? d[5 : 0] = [ 000101 ] = a 2.5 ? baseline p in = 20 dbm p 0.1 28.5 db m settling time (parallel mode) ? start le rising edge > v ih ? end +/ - 0.10 db pout settling ? 15.5 C 16.0 transition t lsb 400 n sec serial clock speed spi 3 wire bus f cl k 10 50 mhz serial setup time from rising edge of vmode to rising edge of clk for d5 a 20 ns clock width clock high pulse width b 10 ns le setup time from rising edge of clk pulse for d0 to le rising edge c 10 ns le pulse le minimum pulse width d 30 ns s pecification n otes : 1 C items in min/max columns in bold italics are guaranteed by test 2 C all other items in min/max columns are guaranteed by design characterization
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 4 rev 2 april 201 4 f1953 datasheet s erial c ontrol serial mode is selected w hen v mode is pulled high (> v ih ) , in serial m ode the f1953 attenuation s etting is programmed via the 3 wire bus (le, clk, data) . in serial mode data is clocked in msb first. note the timing diagram below. note C the idtf1953 includes a clk inhibit feature designed to minimize sensitivity to clk bus noise when the device is not being programmed. when latch enable is high (> v ih ) , the clk input is disabled and data will not be clocked into the shift register. it is recommended that le be pulled high (> v ih ) when the device is not being programmed. s erial r egister d efault c ondition if the device is powered up in serial mode, the device will default to whatever attenuation state is defined by th e six parallel data input pins d 5, d4,d3,d2,d1,d 0 thus allowing any attenuation setting to be specified as the power up state. s erial r egister t iming d iagram : (note the timing spec intervals in blue ) s erial r egister t iming t able interval symbol description min spec max spec units a from rising edge of vmode to rising edge of clk for d5 20 nsec b clock high pulse width 10 nsec c from rising edge of clk pulse for d0 to le rising edge 10 nsec d le minimum pulse width 30 nsec time data word 6 bits d 5 d 4 d 0 d 3 d 1 d 2 8 db clk data data word latched into active register lsb 16 db 1 2 3 4 5 6 7 8 9 4 db 2 db 1 db 0 . 5 db msb le v mode spec interval a b c d polarity : 1 = attenuation switched in 0 = attenuation switched ou t
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 5 rev 2 april 201 4 f1953 datasheet p arallel c ontrol m ode the user has the option of running in one of two parallel modes: direct parallel mode or latched parallel mode . d irect - p arallel m ode : direct - parallel m ode is selected when v mode (pin 1 3) is < v i l and le (pin 5 ) is > v i h . in this mode the device will immediately react to any voltage changes to the parallel control pins [pins 1, 15, 16, 17, 19, 20 ]. use direct - parallel mode for the fastest settling time. l atched - p arallel m ode : latched - parallel m ode is selected when v mo de (pin 1 3) is < v i l and le (pin 5 ) is toggled from < v il to > v ih to utilize latched - parallel m ode: ? set le < v il ? adjust pins [ 1, 15, 16, 17, 19, 20 ] to the desired attenuation setting. (note the device will not react to these pins while le < v il .) ? pull le > v ih . the device will then transition to the attenuation settings reflected by these pins. when the device is powered up in latched parallel mode [ v mode < v i l and le < v il ], the attenuation setting defaults to the state defined by the six parallel data pins [pins 1, 15, 16, 17, 19, 20] l atched p arallel m ode t iming d iagram : (note the timing spec intervals in blue ) l atched p arallel m ode t iming t able : interval symbol description min spec max spec units a serial to parallel mode setup time 100 nsec b parallel data hold time 10 nsec c le minimum pulse width 10 nsec d parallel data setup time 10 nsec d [ 5 : 0 ] data word latched into active register le v mode s pec interval s a d c b
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 6 rev 2 april 201 4 f1953 datasheet t ypical o perating p arametric c urves (evkit loss de - embedded , 3.0 v unless otherwise noted) insertion loss vs. frequency [ a min ] s 11 vs. frequency [t case = +25c, 0.5 db steps ] s 11 vs. attenuation state attenuation vs. freq [t case = +25c, 0.5 db steps ] s 22 vs. frequency [t case = +25c, 0.5 db steps ] s 22 vs. attenuation state - 4.0 - 3.5 - 3.0 - 2.5 - 2.0 - 1.5 - 1.0 - 0.5 0.0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v rf frequency (mhz) insertion loss (db) - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 rf frequency (mhz) rf1 return loss (db) - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v - 900 mhz - 40 degc - 3.0 v - 2000 mhz 25 degc - 3.0 v - 900 mhz 25 degc - 3.0 v - 2000 mhz 100 degc - 3.0 v - 900 mhz 100 degc - 3.0 v - 2000 mhz attenuation setting (db) rf1 return loss (db) - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 rf frequency (mhz) dsa loss (db) - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 rf frequency (mhz) rf2 return loss (db) - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v - 900 mhz - 40 degc - 3.0 v - 2000 mhz 25 degc - 3.0 v - 900 mhz 25 degc - 3.0 v - 2000 mhz 100 degc - 3.0 v - 900 mhz 100 degc - 3.0 v - 2000 mhz attenuation setting (db) rf2 return loss (db)
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 7 rev 2 april 201 4 f1953 datasheet toc s continued ( - 2 - ) phase vs. frequency supply current i dd [vs. temp] input ip3 [f rf = 1 900 mhz , v dd = 3.0 v ] phase vs. attenuation setting supply current i dd [vs. v dd ] compression [f rf = 2000 mhz , attn = 2.5 db ] - 130 - 110 - 90 - 70 - 50 - 30 - 10 10 500 800 1100 1400 1700 2000 2300 2600 2900 3200 3500 - 40 degc - 3.0 v - 0 - 40 degc - 3.0 v - 31.5 25 degc - 3.0 v - 0 25 degc - 3.0 v - 31.5 100 degc - 3.0 v - 0 100 degc - 3.0 v - 31.5 rf frequency (mhz) s 21 phase (degrees) 0.0 0.1 0.2 0.3 0.4 0.5 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v total i dd (ma) attenuation setting (db) 25 30 35 40 45 50 55 60 65 70 75 0 4 8 12 16 20 24 28 32 input ip3 (dbm) attenuation setting (db) - 40c 25c 100c - 110 - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 0 4 8 12 16 20 24 28 400 mhz 900 mhz 1400 mhz 1900 mhz 2400 mhz 2900 mhz 3400 mhz 3900 mhz s 21 phase (degrees) attenuation setting (db) 0.00 0.10 0.20 0.30 0.40 0.50 0 4 8 12 16 20 24 28 25 degc - 3.3 v 25 degc - 3.0 v 25 degc - 2.7 v total i dd (ma) attenuation setting (db) 0.0 0.1 0.2 0.3 0.4 0.5 22 23 24 25 26 27 28 loss compression (db) input power (dbm) - 40degc 2.5 db attn 25degc 2.5 db attn 100degc 2.5 db attn
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 8 rev 2 april 201 4 f1953 datasheet toc s continued ( - 3 - ) dnl [ 400 mhz] dnl [ 900 mhz] dnl [ 2800 mhz] dnl [ 700 mhz] dnl [ 1900 mhz] worst setting dnl - 0.75 - 0.50 - 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) step error (db) - 0.75 - 0.50 - 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) step error (db) - 0.75 - 0.50 - 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) step error (db) - 0.75 - 0.50 - 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) step error (db) - 0.75 - 0.50 - 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) step error (db) 0.00 0.25 0.50 0.75 1.00 400 800 1200 1600 2000 2400 2800 3200 3600 4000 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v worst setting step error (db) rf frequency (mhz)
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 9 rev 2 april 201 4 f1953 datasheet toc s continued ( - 4 - ) inl [ 400 mhz] inl [9 00 mhz] inl [2 9 00 mhz] inl [ 7 00 mhz] inl [1900 mhz] worst setting inl - 1.50 - 1.25 - 1.00 - 0.75 - 0.50 - 0.25 0.00 0.25 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) absolute error (db) - 1.50 - 1.25 - 1.00 - 0.75 - 0.50 - 0.25 0.00 0.25 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) absolute error (db) - 1.50 - 1.25 - 1.00 - 0.75 - 0.50 - 0.25 0.00 0.25 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) absolute error (db) - 1.50 - 1.25 - 1.00 - 0.75 - 0.50 - 0.25 0.00 0.25 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) absolute error (db) - 1.50 - 1.25 - 1.00 - 0.75 - 0.50 - 0.25 0.00 0.25 0 4 8 12 16 20 24 28 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v attenuation setting (db) absolute error (db) - 4.0 - 3.5 - 3.0 - 2.5 - 2.0 - 1.5 - 1.0 - 0.5 0.0 0.5 1.0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 - 40 degc - 3.0 v 25 degc - 3.0 v 100 degc - 3.0 v worst setting absolute error (db) rf frequency (mhz)
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 10 rev 2 april 201 4 f1953 datasheet toc s continued ( - 5 - ) [f rf = 900 mhz] transient [ 15. 5 to 16.0 (msb+) 3.3v f195 3 ] the graphs above show the transient overshoot and settling time performance for both the msb+ and msb - cases for the f195 3 . th e device settles very quickly ( ~ 400) nsec with benign (~0.5) db overshoot . transient [ 15. 75 to 16.00 (msb+) standard dsa ] transient [ 16.0 to 15.5 (msb - ) 5.0v f195 3 ] the graphs below show the transient overshoot and settling time performance for a popular competing dsa. n n o o t t e e t t h h e e o o v v e e r r s s h h o o o o t t / / u u n n d d e e r r s s h h o o o o t t e e x x c c u u r r s s i i o o n n o o f f a a l l m m o o s s t t 1 1 0 0 d d b b and the very long settling time. for the msb - case, the settling time is off the scale, ~ 3 usec. transient [ 16.00 to 15. 75 (msb - ) standard dsa ] - 1.0 - 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 - 10.9 - 9.9 - 8.9 - 7.9 - 6.9 - 5.9 - 4.9 - 3.9 - 2.9 - 1.9 - 0.9 0 100 200 300 400 500 600 700 800 le trigger (volts) envelope power (dbm) time (nsec) glitch ~ 0.5 db pwr (dbm) trigger settling time = 400 nsec (+/ - 0.1 db) - 1.0 - 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 - 15.20 - 14.20 - 13.20 - 12.20 - 11.20 - 10.20 - 9.20 - 8.20 - 7.20 - 6.20 - 5.20 - 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) pwr (dbm) trigger settling time = 600nsec (+/ - 0.1 db) - 1.0 - 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 - 11.0 - 10.0 - 9.0 - 8.0 - 7.0 - 6.0 - 5.0 - 4.0 - 3.0 - 2.0 - 1.0 0 100 200 300 400 500 600 700 800 le trigger (volts) envelope power (dbm) time (nsec) glitch ~ 0.3 db pwr (dbm) trigger settling time = 370 nsec (+/ - 0.1 db) - 1.0 - 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 - 13.57 - 12.57 - 11.57 - 10.57 - 9.57 - 8.57 - 7.57 - 6.57 - 5.57 - 4.57 - 3.57 - 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) pwr (dbm) trigger settling time >> 1 usec
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 11 rev 2 april 201 4 f1953 datasheet p in d iagram clk data d 0 d 1 d 3 g n d [ i n t e r n a l n c ] v mode gnd [ internal nc ] d 4 le gnd [ internal nc ] * rf 2 * rf 1 d 2 d 5 exposed pad v d d n c g n d [ i n t e r n a l n c ] 2 1 3 5 4 package drawing 4 mm x 4 mm package dimension 2 . 06 mm x 2 . 06 mm exposed pad 0 . 5 mm pitch 20 pins 0 . 75 mm height 0 . 25 mm pad width 0 . 55 mm pad length 12 11 13 15 14 6 7 9 8 10 16 17 19 18 20 n c n c c o 0 . 3 5 m m top view ( looking through the top of the package ) * device is rf bi - directional
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 12 rev 2 april 201 4 f1953 datasheet p ackage d rawing ( n c g20 4 x 4 2 0 pin )
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 13 rev 2 april 201 4 f1953 datasheet p in d escriptions pin # pin name pin function 1 d 5 16 db attenuation control bit. pull high for 16 db attn. 2 rf1 device rf input or output (bi - directional) . internally dc blocked . 3 data serial interface data i nput. 4 clk serial interface clock input. 5 le serial interface latch e nable input. internal pullup (100k ohm). 6 vdd power supply pin . 7 nc internally unconnected . 8 nc internally unconnected . 9 nc internally unconnected . 10 gnd connect to ground . (this pin is internally unconnected) 11 gnd connect to ground . (this pin is internally unconnected) 12 gnd connect to ground . (this pin is internally unconnected) 13 vmode pull high for serial mode. ground for parallel control mode . 14 rf2 device rf input or output (bi - directional). internally dc blocked . 15 d 4 8 db attenuation control bit. pull high for 8 db attn. 16 d 3 4 db attenuation control bit. pull high for 4 db attn. 17 d 2 2 db attenuation control bit. pull high for 2 db attn. 18 gnd connect to ground . (this pin is internally unconnected) 19 d 1 1 db attenuation control bit. pull high for 1 db attn. 20 d 0 0.5 db attenuation control bit. pull high for 0.5 db attn. ep exposed paddle connect to ground with multiple vias for good thermal relief .
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 14 rev 2 april 201 4 f1953 datasheet ev kit s chematic the diagram below describes the recommended applications / evkit circuit:
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 15 rev 2 april 201 4 f1953 datasheet evk it o peration (email: rfsupport@idt.com to request an evkit and controller) the picture and graphic below describe how to operate the evkit rf1 dc power serial control port unused rf2 data clock latch enable set to - to use dip switch set to + to use serial port 0.5 db lsb 16 db msb
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 16 rev 2 april 201 4 f1953 datasheet evk it bom ( f1953 ) t op m arkings f1953 bom rev 01 pcb rev 01 item # value size desc mfr. part # mfr. part reference qty 1 10nf 0402 cap cer 10000pf 16v 10% x7r 0402 GRM155R71C103KA01D murata c2,12 2 2 0.1uf 0402 cap cer 0.1uf 16v 10% x7r 0402 grm155r71c104ka88d murata c1,11 2 3 header 2 pin th 2 conn header vert sgl 2pos gold 961102-6404-ar 3m j5,7 2 4 header 4 pin th 4 conn header vert sgl 4pos gold 961104-6404-ar 3m j8 1 5 header 8 pin th 8 conn header vert sgl 8pos gold 961108-6404-ar 3m j6 1 6 sma_end_launch .062 sma_end_launch (small) 142-0711-821 emerson johnson j2,3,4 3 7 0 0402 res 0.0 ohm 1/10w 0402 smd erj-2ge0r00x panasonic r1-7,12,c13,c14 10 8 3k 0402 res 3.00k ohm 1/10w 1% 0402 smd erj-2rkf3001x panasonic r9-11 3 9 10k 0402 res 10k ohm 1/10w 1% 0402 smd erj-2rkf1002x panasonic r8,15-17 4 10 100k 0402 res 100kohm 1/10w 1% 0402 smd erj-2rkf104x panasonic r13 1 11 267k 0402 res 267k ohm 1/10w 1% 0402 smd erj-2rkf2673x panasonic r14 1 12 dipswitch th 10 8 position dip switch kat1108e e-switch u1 1 13 digital step attenuator f1953z f1953z idt u2 1 14 pcb pcb rev 01 f1953s evkit rev 01 sbc 1 15 100pf 0402 cap cer 100pf 16v 10% x7r 0402 GRM155R71C103KA01D murata c3-10,15-20 dnp 16 sma_end_launch .062 sma_end_launch (small) 142-0711-821 emerson johnson j1 dnp total 33 11/15/2012 i d t f 1 9 5 3 n c g i z 1 3 0 4 a b a p a r t n u m b e r d a t e c o d e [ x y y w w x x x ] ( w e e k 0 4 o f 2 0 1 3 )
6 - bit digital step attenuator 400 to 4000 mhz idtf1953 glitch - free tm digital step attenuator 17 rev 2 april 201 4 f1953 datasheet evk it t hrough - r eflect - l ine ( trl ) c alibration the through - reflect - line (trl) method [1] is used to de - embed the evaluation board losses from the s - parameter measurements of the f1953 . this method requires the use of three standards: a through, a reflection, and a line. the trl method has the advantage over other calibration methods in that it r equires only one of these three standards to be well defined. the trl through which is used for the f1953 trl calibration was constructed identically to the evaluation board, minus the dut and its corresponding length. therefore, the through correspond s t o a precise zero length connection between the input and output reference planes of the dut. this through satisfies the requirement of the trl method that one of the three standards be precisely specified. the trl reflection standard used is constructed i dentically to the input and output lines of the evaluation board, with a short placed at the reference plane of the dut. in accordance with the trl methods requirements, the actual magnitude and phase were not accurat ely specified, but the phase was known to within 90 degrees and the trl reflection standard has a magnitude close to one. the trl line standard is identical to the trl through, but with an additional length of 0.8 inches (2 cm). this satisfies the trl methods requirement that the trl be a di fferent length than the trl through, that it have the same impedance and propagation constant as the through, and that the phase difference between the through and the line be between 20 degrees and 160 degrees. the difference in lengt h yield s a phase diff erence of approximately 20 degrees at 500 mhz, and a phase difference of 160 degrees at 4 ghz. standards used for f195x trl calibration f1953 evaluation circuit engen , g.f.; hoer, c.a.; thru - reflect - line: an improved technique for calibrating the dual six - port automatic network analyzer, ieee transactions on microwave theory and techniques , volume: 27 issue:12, pp. 987 C 993, dec 1979.

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